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resume mixed signal 109 Pleasant street. Auburn, CA 93010. Motivated and versatile Electronics Engineer specializing in analog design and Visual Basic. Xena Electronics, Woodland, CA. STRATEGIC MARKETING ENGINEER. DESIGN AND DEVELOPMENT ENGINEER.

Xena Electronics developed cellular products such as hands-free kits for writing paper, cellular phones and Wireless Local Loop WLL . Designed an Automatic Test Equipment ATE stand that tested a number of ORA s products such as hands-free kits and WLL. The stand consisted of a 11X17 two layer board stuffed with numerous analog and digital circuits including a power supply and 8051 processor. The board interfaced to an I/O board inside the PC. Wrote and designed a self test and calibration program for the ATE, including a routine to output the same amplitude sine wave regardless of Essays, which ATE board or PC was used. Wrote numerous Visual Basic programs to make the ATE versatile enough to 100 test a number of products and simple enough to use that anyone could run the my research mercedes, test stand with minimal training.

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Built the writing, first ATE. Chose the IBM PCs and Daytronics computers, designed the analog interface cards including servo control loops , and wrote all the software. End product was an ATE stand that could perform more complex tests than previously possible, with the added bonus of having automatic shut down and data logging capabilities with data being transferred through the Ethernet to the VAX for report monitoring . Five additional stands were later built. Developed Electronic Control Units for papers paul analysis, both in house and for customers consisting of my research, servo control loops composed of the position, velocity, and acceleration signals to control hydraulic servomotor based stands. Designed a circuit, based on LaPlace Transforms that would modulate a high voltage 400 Hz signal in order to genetic engineering writer, test a lead lag circuit inside an Aircraft Generator Control Unit. This enabled the vendor, Bendix to electronically test the units by obtaining a Bode Plot using a HP3562 Dynamic Signal Analyzer. Mercedes. Used AUTOCAD to draw electronic schematics. Designed analog circuits as needed such as LVDT signal conditioner and Linear Power Supplies. MBA from California Lutheran University, Thousand Oaks, CA . Forty three semester hours of cheap feasibility, post graduate courses in mercedes electronics and online, computer science including C, C++, Visual Basic, Pascal, and mercedes, Assembly. BSEE from Ohio State, Columbus, OH.

Professional Engineers License in Electrical Engineering, State of genetic engineering essay writer, California. References are available upon paper request from former supervisors. Personal Computer expert. Analog /Mixed-Signal Design Engineer position emphasizing design and development for write my essay rice, deep sub-micron analog circuits, PLLs, VCOs, and mixed signal circuits. Design Logic, San Antonio, TX, USA. November 2001 - Present. Working as a Design engineer in the PLL Design Group, with responsibilities in writing my research PLL design, Supervision of Layout, Silicon Debug Characterization of papers online paul analysis, PLL. Designed a PLL for DSP Processor. Designed a PLL for DSP processor, in 0.18um technology, working at 1.8V .The VCO output frequency range was from my research paper, 300Mhz to 400MHz.

The input frequency range was from 11.289MHz - 27MHz. The PLL used a current starved ring oscillator. My major responsibilities were the design and simulations of the individual PLL blocks using H-spice, closed loop simulations using AMS Antrim Mixed Simulator , stability analysis using a macro-model of cheap, PLL, and post layout simulations with extracted parasitics using Arcadia. Designed and Debugged a PLL for 192KHz Digital Audio Interface Receiver. Designed PLL for writing my research, Audio Applications in 0.35um technology, working at Essays 3.0V . The VCO output frequency range was from 8Mhz to 50MHz. The input frequency range was from 8KHz - 192KHz. Paper Mercedes. The PLL used a relaxation type Oscillator, PFD, charge-pump, band-gap current source, and critical essay, bias current generator.

Also designed a frequency detector for the same chip, which detects whether the input sample rate frequency is my research mercedes, greater or lower than 96KHz. - My major responsibilities for this PLL were block level simulations using H-spice, closed loop simulations using AMS Antrim Mixed Simulator , stability analysis using macro-model of PLL, and post layout simulations. Debugged the PLL using an AP BOX, network analyzer, and Time Interval Analyzer TIA , Micro-probe station, Therostream. Made set-up for chip level simulation using AMS Antrim Mixed Signal Simulator . Successfully simulated Audio Receiver Chip , which includes PLL, digital logic, pads. - Major challenges were to keating analysis, interface between digital logic and analog blocks. Characterized and Debugged a PLL for 96KHz Digital Audio Interface Receiver. Characterized the performance of a PLL over temperature and voltage. Writing. RMS Cycle-Cycle Jitter, VCO gain, Time Deviation were the major things to paul, observe. Synopsis, Gurgaon, Haryana, India. July 1999 - October 2001.

Designed a PLL for Cell-Phone Applications. Designed and characterized a PLL in writing my research paper silicon for a cellular phone chip in my essay facial 0.13u working at 220Mhz. Designed of current reference, current-controlled oscillator, DAC and PFD. The purpose of current reference block was to provide a reference current to writing my research mercedes, DAC and VCO. The 5 bit DAC was to humans essay, generate an paper output current corresponding to the setting of the input bits, which in solving essay turn controlled the frequency of the VCO. Variations on the output current of current reference block due to power supply, temperature and writing paper mercedes, process were very small. DAC is voltage to current converter and genetic humans essay writer, the output current has binary weight according to input bit.

All the blocks were simulated in both SSIM and BSIM models. To know the writing paper, dynamic behavior of writer monitoring, PLL digital and my research paper, analog blocks are simulated in mixed signal environment Verimix . Write Study About Rice Facial. My responsibility was to setup for interface between digital and paper mercedes, analog blocks. Digital simulations were performed using Verilog-XL and the analog simulations were done in write my essay feasibility facial mask SPICE. Custom Layout Integration of Analog blocks. Experience in full custom layout of writing paper, a current reference, DAC, and rice facial, VCO for a PLL in my research paper 0.18u.

Experience in website floor planning and integration of writing my research paper, analog blocks. Also checked out writer monitoring GDSII for my research, TESTCHIP for process qualification. This included all analog blocks with other structures like op-amps and voltage references. Also was responsible for post layout simulations using STAR-RC for essay writer website, parasitic extraction. Topology selection for writing my research paper, analog circuit design and design of various Op-amps Proposed and implemented a methodology for genetic essay writer, analog design automation. My Research. Circuits used to cheap analysis, verify the proposed methodology were CMOS OTA , folded cascode OTA, and Miller compensated OTA. Depending upon knowledge base and Specifications given by the user. Writing My Research Paper. The tool gives first hand sized-schematic diagram from the given user specifications. Papers Online Keating Analysis. The source code was written in C.

Indian Institute of Technology IIT , Kanpur, India. Masters Kanpur, UP, India. Electrical Engineering Microelectronics and VLSI Design. Regional Engineering College REC. June 1998 Bechlors Hamirpur, Himachal, India. Electronics Communication Engineering. SPICE. PowerMill Synopsis circuit simulator . AMS Antrim mixed signal Simulator . Writing My Research Paper Mercedes. MATLAB. And Creative. Virtuoso Cadence Layout Schematic Editor . Verimix Cadence Mixed Signal Simulator . Avanti Hercules Mentor Caliber DRC LVS . StarRC Post Layout Arcadia Synopsis parasitic extraction . Languages - Verilog.

Full-custom analog and digital layout in submicrons and paper, bicmos technologies. Support and training of youngs layouters. Designer assistant for simulation of modified bloks. Papers Online Keating Analysis. PCB drawing with third generation cellular phone constraints. Writing My Research Paper. Design and programmation of PCB for testing ASICs with GPIB driving on earthquake, labview 5. Writing Mercedes. VHDL auto-training for system simulation assistant . Re-layout of a complete FPGA for use in radiation environment. Layout full-custom of regulators for multiple use in multiple technologies. Software: Cadence, calibre, dracula and L.E.D. on Solaris workstation. Apr 2000 - Dec 2000. Layout of a PCB for develop the third generation of cellular phones.

Software: Mentor Graphics on Solaris workstation. Jul 1999 - Feb 2000. Full-custom layout of mixed signal bloks in and creative problem essay sub-micron and bicmos technologies. Design of PCB for testing the asics with GPIB driving on labview 5. Writing My Research Paper Mercedes. VHDL auto-training for online earthquake, system managment. Software: All tools of Mentor Graphics on my research paper, Solaris workstation. Jan 1999 - Jun 1999. Development with Pspice 7 of an ASIC in gate array technology. DM Microelectronic SA. Clean room operator in masking division week-end job . 1996 to 1997 - Technician in microelectronics equivalent to MSEE in cheap northridge earthquake microelectronic. 1994 to 1996 - Technician in electronics equivalent to BSEE in electronic. 1991 to my research mercedes, 1994 - Electronician needed for BSEE training.

Diploma delivered by the Centre de formation Professionnel du Littoral Neuch telois C.P.L.N. in Switzerland. References available upon request. Daniel A. Clifford. 1372 Andover Rd. Rockford, IL 60119. Position as an electrical engineer, with interests in ASIC design, digital and analog circuit design, and embedded software. Iowa State University, Ames, Iowa 1991 to 1995. B.S., Electrical Engineering, December 1995. Experience in digital circuit design, including Intel x86 and papers cheap analysis, i960, ARM, and Rockwell AAMP processors; PCI and writing paper, AMBA buses; serial links including Fibre Channel, Infiniband, ethernet, LVDS, RS232, and buy essay online cheap northridge earthquake, various ARINC protocols; SRAM and writing my research paper mercedes, DRAM buses SCSI PLD logic design Analog circuit design including active analog filters, amplifiers, and power circuitry Experience with circuit simulation tools, including P-Spice and Saber C, C++, VB, Ada, Assembly, Verilog, and VHDL Experience with Boundary Scan JTAG Experience with Synopsys simulation and genetic essay writer, synthesis tools Schematic capture with Viewlogic and Accel. Lowell Communications, Little Falls, MN. Worked on embedded SCSI controller ASIC.

The design included integration of an ARM processor, ARC DSP, SCSI controller, and various peripherals, including interrupt controller, timers, etc. The ARM was the main microprocessor, communicating over an AMBA bus to the various peripherals. ASIC design was done in Verilog, using Synopsys tools. Code written in writing mercedes C, assembly, and Verilog to test ARM and peripheral functionality. Low level work done on JTAG to test In Circuit Emulator ICE functionality. High speed 1 GHz + digital and analog design for Fibre Channel applications. Implementation of embedded systems. Humans Essay Writer. Systems are centralized around one or more ASIC s which implement high-speed switching of Fibre Channel data. The ASIC sends and receives parallel data streams through serializer/deserializers SER/DES , which serialize the data and send it to the outside world. Paper. My part includes timing and logic analysis of the ASIC to ensure proper operation with the SER/DES and other ASIC s. The system is cheap study rice facial, managed by an embedded PC-based supervisory system. My part with this included mating the PC to on-board PCI devices and other memory and I/O devices.

Wrote PLD glue logic to interface peripheral devices to the PC. Aided in writing and debugging software drivers for these devices. Perform timing analysis for my research paper, all interfaces. Developed an cheap write feasibility study about rice facial in-circuit PROM programmer through a JTAG port. Cyberlogic Engineering, Alexandria, Minnesota. PLC logic programming and Human-Machine Interface programming.

PLC coding to automate food, beverage, and my research paper, animal feed production facilities. HMI programming with Wonderware to develop user-friendly interfaces to My Dream, production lines and machines. Writing My Research Mercedes. Program Management and Field Support. Maxim Collins Inc., Cedar Falls, Iowa. Electrical Engineer with the Custom Test Equipment group. Design of online paul, automated test equipment ATE s for commercial avionics. The ATE s were used to automate the my research mercedes, test of humans writer, commercial avionics, for my research, factory production test and service center debug and support. Also wrote code to operate these ATE s in lab and My Dream House, factory environments. The code would control test instruments over GPIB, VXI, RS232, and other interfaces.

Specialized in processor bus emulation and test . Designed processor bus interface circuit cards to connect a processor bus to an emulator. Mercedes. This included research into processor bus transactions and timing, digital and analog hardware design, logic design, simulation using P-Spice and Essays, Saber , board layout, and paper, debug. Developed cards to test Intel x86, Texas Instruments DSP, Rockwell AAMP processor buses and all associated memories and peripherals. Did much work with Boundary Scan JTAG test development . Write My Essay Feasibility Rice Facial Mask. This included writing applications in C and C++ to execute tests. These tests exercised the primary processor, PLD, and writing paper, ASIC components of a board, along with direct or indirect test of other peripheral devices not directly attached to the Boundary Scan Chain. Analog design, including filtering and wave shaping . Also included utilizing techniques for noise control in analog and digital systems. Alpha Sigma Phi Fraternity: Vice President and Academic Chair. Dean s list every semester at Iowa State. Tau Beta Pi, Eta Kappa Nu, Phi Kappa Phi, and Golden Key Honor Societies. 125 Colonial Street, Apt.

215. Dayton, OH, 45701. Design/test engineer or researcher position in the area of analog, digital and House, mixed-signal VLSI design and test. Sep. 1998 Present. School of Electrical Engineering and Computer Science. Ohio University, Dayton, OH, USA. Dissertation: Analog and mixed-signal test and fault diagnosis.

Expected Graduation Date: Spring or Summer 2002. Sep.1993 Jul. 1996. Weak Signal Detection Lab, Institute of Physics, China Academy of my research paper, Sciences,Beijing, P.R.China. Sep. 1989 Jul. 1993. Department of Electrical Engineering Automation, Tianjin University, Tianjin, P.R.China. Carter Research Associateship, EECS, OU.

Project: Analog and mixed-signal test and essay writer website monitoring, fault diagnosis Skills: Analog and writing mercedes, mixed-signal test, Analog simulation, VHDL design, VLSI CMOSdesign and test. Electronics and Electrical Engineering Lab, National Institute of Standards and Technology, Cleveland, OH. Project: Testing strategies for mixed-signal systems with embedded software Skills: Analog and papers cheap keating, mixed-signal test, analog simulation, data acquisition by GPIB and Labview. Arthur Test Control Technology Co. Ltd., Beijing, P.R.China. Responsible for designing and constructing the STS2106A MS/LS Digital IC Test System. Writing Mercedes. Skills: Board-level analog and mixed-signal design, layout, debug, test. Digital design with EPLD devices, digital IC Test.

Digital ATE maintenance as application engineer. Weak Signal Detection Lab, China Academy of Sciences, P.R.China, Project The design and critical and creative problem solving, construction of part of writing my research paper, ECS for write my essay, low temperature scanning tunneling microscope, supported by China National Science Foundation. Skills: Low-noise analog design, layout and test, pre-amplifier design, feedback control design. Dept. of paper, EE, Tianjin University, P.R.China. Project: An algorithm for the computation of power analysis in power systems by Fortran77. 1989 Tianjin University Distinguished New Student Award.

Tianjin University Outstanding Student Scholarships in 1990, 1991, 1992. 1996 Institute of Physics Outstanding Graduate Students Award Nominee. 2002 Ohio University Outstanding Graduate Student Award Nominee in process . 4+ year experiences in website board-level digital, analog and mixed-signal design including 2-year industrial experience. 2 year industrial experiences in digital IC test; 2 year experiences in low-noise analog design and writing my research paper mercedes, feedback control design. 4+ year experiences in schematics, synthesis, simulation, test, place route, verification. Critical Essay. 4 year experiences in writing paper mercedes analog and mixed-signal test and fault diagnosis; Excellent writing communication skills and team-work ability. Languages: C/C++, Fortran, Assembly Language, Basic, JAVA, Matlab, Labview, VHDL; Hardware Debug: Logic analyzer, Oscilloscope. Circuit Schematic Tools: OrCAD, Tango, Protel, CADSTAR; Analog Simulation Tools: Spice, Saber.

VHDL design by My Dream Active-VHDL and implemented by XILINX FPGA. Digital design by ALTERA Max+Plus II and implemented by MAX7000 EPLD devices. VLSI transistor-level CMOS Design and my research, Test by Mentor Graphics: Design Architect, QuickSim, ICStation, Lsim, AccuSim, AutoLogic, Leonardo, BISTA, ATPG, AutoLogic II, QuickFault, QuickGrade, QuickSim, QuickPath. Brendan Harrison, Kang Qinghong, Carl Webster and Bryan Barrett, Nonrandom quantization errors in timebases, IEEE Transactions on cheap write study facial, Instrumentation and my research paper, Measurement, vol. 50, pp. 888-892, 2001. Kang Qinghong, Carl Webster, A generalized fault diagnosis in dynamic analogue circuits, International Journal of Circuit Theory and Applications, vol.30, no.4, 2002. Carl Webster, Kang Qinghong, Zhi-Hong Liu and Jerzy Rutkowski, Entropy-based optimum test points selection for analog fault dictionary techniques, submitted to My Dream House Essays, IEEE Transactions on Instrumentation and Measurement. Carl Webster and writing my research mercedes, Kang Qinghong, Generalized decomposition method by write about facial multiple-measurement and paper, multiple-frequency for analog fault diagnosis, submitted to IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications.

1. Brendan Harrison, Kang Qinghong, Carl Webster and Bryan Barrett, A new method to website monitoring, compensate quantized time-base nonlinearity of sampling instruments, Workshop on Software Embedded Systems Testing, National Institute of Standards and Technology, Gaithersburg, MD, Nov. 1999. 2. Brendan Harrison, Kang Qinghong, Carl Webster and Bryan Barrett, Nonrandom quantization errors in timebases, Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference, vol. 1, pp. 235-240, Baltimore, MD, May 2000. 3. Carl Webster and Kang Qinghong, A method for multiple fault diagnosis in analog circuits, Proceedings of the 33rd Southeastern Symposium on System Theory, pp. 65-68, Dayton, OH, Mar. 2001. 4. Writing My Research Paper. Carl Webster and Kang Qinghong, Multiple-fault diagnosis of analog circuits by thinking and creative essay locating ambiguity groups of paper, test equation, Proceedings of the IEEE International Symposium of Circuits and papers online cheap keating analysis, Systems, vol. My Research. 5, pp. 199-202, Sydney, Australia, May 2001.

5. Online Northridge. Carl Webster and Kang Qinghong, A new approach to multiple fault diagnosis in linear analog circuits, Proceeding of the 7th IEEE International Mixed Signal Testing Workshop, Atlanta, GA, Jun. Writing Mercedes. 2001. 6. Carl Webster and Kang Qinghong, Multiple fault diagnosis of analog circuits based on large change sensitivity analysis, the Proceedings of the 15th European Conference on Circuit Theory and Design, Espoo, Finland. Aug. Engineering Essay. 2001. 7. Carl Webster and writing paper mercedes, Kang Qinghong, A decomposition method for analog fault location, accepted by buy research papers cheap paul keating analysis the IEEE International Symposium of Circuits and Systems, Scottsdale, Arizona, USA, May 2002. 8. Carl Webster and Kang Qinghong, Locating stuck faults in writing paper analog circuits, accepted by the IEEE International Symposium of Circuits and Systems, Scottsdale, Arizona, USA, May 2002. Engineering and Design of Analog and Digital Electronics, Controls and Embedded Systems. Contract engineering and consulting services for the electronics industry.

Objective area includes, but is not limited to, the Northeastern United States (CT, N-DE, MA, NE-MD, NJ, NY, PA, RI). Scope involves all phases of papers cheap keating, engineering, development and design of analog and digital electronic equipment, controls and embedded systems for writing my research paper mercedes, industrial and commercial applications. CONCOR SYSTEMS, INC., Syracuse, New York. Responsible for Product Development, Consulting and System Engineering of electronic hardware and microprocessor or microcontroller based controls and systems for various clients. HIGHLIGHTS OF ACHIEVEMENTS AT CONCOR SYSTEMS.

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A generic digital telco interface could be provisioned to operate as a T1, E1, or ISDN Pri interface. A generic analog telco interface could be provisioned to operate with commonly used 2-wire or 4-wire special services or POTS lines. Generic hardware would also have the advantage of reduced inventory burden. Bachelor of Science Electrical Engineering Texas AM University, 1987 - 1991. Electromagnetic Theory Applied Electromagnetics Microwave RF Circuits System Design Analog Digital Communications Theory Digital Signal Processing Digital Analog Circuit Design C Language Programming. Digital Voice Telephony Link Infrared Pulse Train Detector/Decoder Log Periodic Array Wideband Directional Antenna Computer Modeling for Microstrip Filters 2.4 GHz Micro-strip Bandpass Filter. 1270 Indian Trail Road. Director of engineering in electronics firm. A proven technical manager with an excellent educational background.

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MANAGER OF DEPLOYMENT ENGINEERING. Apple Tree, Inc., Sacramento, CA 3/91 - 10/95. DIRECTOR OF ENGINEERING. Safe Microwaves, Inc., Sacramento, CA 2/86 - 2/91. Xtron Systems, Inc., San Diego, CA 11/83 - 1/86.

Epkot Aircraft Co., San Jose, CA 6/81 - 10/83. MEMBER OF TECHNICAL STAFF. SAP, SPICE, Microcap, Orcad, ABEL, VHDL, Autocad Lite, MathCad, FileMaker Pro, Basic, DOS, Windows, Microsoft Office including Word, Excel, Project, Access and PowerPoint. PROFESSIONAL DEVELOPMENT PROGRAMS. Mastering Management, Santa Clara University. Approvals Liaison Engineer, British Approvals Board for Telecommunications. Member Technology Association of Georgia. Masters of Business Administration - Emory University, Atlanta, GA - graduation May 2002. Master of Science, Electrical Engineering - University of California Los Angeles. Bachelor of Science, with honors, Engineering - California Institute of Technology, Pasadena, CA. Co-Valedictorian - Paso Robles High School, Paso Robles CA.

17 Redmond Drive. Tacoma, WA 98034. RF/Optical/High-Speed-Analog Engineering position requiring high-frequency/low-noise/broadband hardware design and/or RF system level definition. Master of Science in Electrical Engineering/Minor in Mathematics, Washington State University WSU , August 1993, Grade Point Average GPA 3.89 of 4.0, Specialized in Electromagnetics and Semiconductor Theory. Bachelor of Science in Electrical Engineering, WSU December 1989, GPA 3.56 of study about rice facial mask, 4.0, Cum Laude, Four Presidential Honors for writing, high GPA levels. Terrace Corporation, Bremerton, WA. July 2000 to July 2002. Responsible for design of My Dream House Essays, transmitters/receivers ranging in data rates from 125 Mb/s to 2.5 Gb/s. Data channel receivers utilized InGaAs Indium Gallium Arsenide and silicon APD s Avalanche Photo Diodes with sensitivities in the range of -48 dBm for 125 Mb/s data and -38 dBm for 1.25 Gb/s data optical power levels . APD receivers required high voltage circuit design 60 volts for 1550 nm to my research paper mercedes, 200 volts for 800 nm with temperature compensation. Another low frequency receiver design utilized a germanium quad cell for purposes of tracking and alignment of the genetic engineering, system optical transceiver heads; this design utilized an extremely low noise amplifier chain with AGC Automatic Gain Control . Transmitter designs utilized Fujitsu/Agere DFB Distributed Feedback lasers in butterfly package feeding an paper mercedes EDFA Erbium Doped Fiber Amplifier amplifier.

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May 1999 to June 2000. Principal RF Engineer. Responsible for next generation 2.5 Gigabit/s data rate, 100 picosecond rise/fall times fiber optic transceiver development utilizing VCSEL Vertical Cavity Surface Emitting Laser multimode, 850 nm wavelength transmitter, high frequency optoelectric PIN diode receiver assemblies, 2.5 Gb/s GaAs Serializer/Deserializer chips. Project involves extensive use of the following software/hardware tools: Agilent ADS software, high frequency SPICE simulations, PADS schematic/PCB layout software, Hewlett Packard 3.2 Gigabit/s jitter analysis system including BERT Bit Error Rate Tester , Agilent 83480 high speed sampling scope 20 GHz front end bandwidth with 83487A 2.8 GHz optical/electrical converter plug-in and my research, HP54751A TDR plug-in, Advantest optical power meter, JDS Fitel optical attenuator. Eye diagram analysis, BER analysis 10e-12 BER goal , jitter analysis are the mainstay performance indicators. Also, high speed 3.2 Gb/s, 100 picosecond rise/fall times backplane design for high port-count Fibre Channel switch. Backplane design requires: extensive modeling of thinking and creative solving essay, vias, couplers, connectors, transmission line geometries with HFSS High Frequency Structure Simulator software from both Ansoft version 7.0 and Agilent version 5.5 high frequency SPICE-like simulations using Agilent ADS software evaluation of high speed connectors from Teradyne VHDM and my research mercedes, HSD , AMP HS3 , Siemens SpeedPac , FCI/Berg Metral . United Communications Corporation, Lynnwood, WA. September 1997 to online, April 1999.

Principal RF Engineer. Involved with skunkworks GSM Smart Antenna system effort. Project included travel to the U.K. for training/consulting time with a GSM organization called MAC Multiple Access Communications . Responsible for system RX and TX RF Hardware development including the following: RX side RF switch matrix four RF inputs and 12 RF outputs with drop-in, all surface-mount RF components M/A Com LNA s, Alpha splitters/digital attenuators/GaAs switches for operation in either the EGSM, DCS-1800, or PCS-1900 frequency bands. Writing Mercedes. Design included the following: an engineering humans essay writer Altera EPF10K20 programmable logic device for control of all switching functions in accordance with the GSM TDMA format, a pilot tone and RF detector circuitry for path integrity checks, digital attenuators on all RF paths for path gain balance to within 0.5 dB. Paper Mercedes. The entire receive side noise figure, gain, and intercept point were set by essay website this design. Writing Mercedes. 12 layer FR-4 PCB. uplink scan receiver essentially a narrowband, IF-digitized digital receiver with drop-in RF components for all three frequency bands mentioned above.

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February 1994 to June 1995. System Test Engineer. International Sensor Technology is a small, family-owned business originating from PhD s Laser-Heated Thermoluminescent Dosimetery LHTLD patent; Naval contract to deliver ship and shore radiation badge readers: The system used SYNRAD CO2 lasers to locally heat an writing irradiated phosphor personnel dosimeter ; the heated phosphor would emit photons with photon density proportional to the radiation level; a high voltage photomultiplier tube gathered the buy essay online cheap earthquake, photons and translated them into my research paper, electronic pulses for dosimeter dosage measurement. I was responsible for electronic debug, calibration, troubleshooting, and accuracy testing of both ship and shore systems. Washington State University, Everett, WA. August 1991 to May 1993. This position required grading course-work/exams, supervising laboratory experiments, giving course lectures, research in non-linear MOSFET characteristics, one-on-one tutoring of students in courses covering Electromagnetics, Control Theory, Digital circuits. The position was with the Electrical Engineering Department and write feasibility rice mask, covered educational costs associated with my Master s degree as well as providing a salary. Naval Engineering Station, Shelton, WA. February 1990 to August 1991.

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Development of test fixtures and detailed test plans. Quality control and customer liaison as required. The Johns Hopkins University, Baltimore, Maryland. Bachelors of Science in writing my research paper Electrical Engineering, May 1992. Catonsville Community College, Catonsville, Maryland. Associate of Arts in Electronic Technology, May 1987. Certificate in Digital Electronics, May 1987.

Harford Community College, Churchville, Maryland. Associate of House, Arts, May 1978. REFERENCES FURNISHED UPON REQUEST. Department of Electrical Computer Engineering. Montgomery University, AL. ECE Dept. Montgomery University, Montgomery, AL, Current. Ph.D Candidate, Graduation scheduled in 2002, Summer Dissertation finished. Major area: Power Electronics.

Minor area: Control Systems. People University of Science and Technology, Harbin, China, June 1997. M.S., Electrical Engineering. People University of Science and Technology, Harbin, China, July 1993. Diploma, Electrical Engineering. Arts of modern power supply, UPS, ballast, motor drive, embedded control system and IC design related to power supply system, magnetic components, modeling, control, simulation, topologies, soft switching techniques for inverters and converters, power factor correction, motion control, etc. Department of Electrical Computer Engineering, Montgomery University. Research Assistant and Ph.D student.

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